1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
For example, the conventional methods of manufacturing a semiconductor device are disclosed in Japanese Laid-Open patent publication Nos. 2002-190520 and 2000-235973.
In the above conventional methods of manufacturing a semiconductor device manufacturing methods, an antireflection film is provided on an aluminum interconnection which is a lower layer, a plasma nitride film which works as a stopper during etching is formed on the antireflection film, and an interlayer film which is an insulating film is formed on the plasma nitride film. When a via is formed in the insulating film, first etching is performed on condition that etching selectivity can be ensured between the insulating film and the plasma nitride film. Then, the plasma nitride film is overetched in second etching to make a via hole from which the antireflection film is exposed.
An example of the conventional semiconductor device is disclosed in Japanese Laid-Open patent publication No. 2002-319620. FIG. 8 is a view for explaining a method of making a contact hole shown in Japanese Laid-Open patent publication No. 2002-319620. In the method of making the contact hole, dry etching is performed by using a resist 34 as a mask, and thereby a contact hole 38 is made in a thick insulating interlayer 32 on a lower diffusion layer 24 formed on a surface of a silicon substrate 22 while a contact hole 36 is made in a thin insulating interlayer 32 on a lower interconnection layer 26 formed on an oxide layer 30. Although only the insulating interlayer 32 is etched in making the contact hole 38, the insulating interlayer 32 and an etching delay layer 28 are etched in making the contact hole 36. Then, the resist 34 is removed and post-dry-etching treatments (cleaning and the like) are performed (not shown).
Reactive ion etching in which anisotropic etching can be performed is used as the dry etching in making the contact holes 36 and 38. This is because the anisotropic etching is desirable in making the contact holes 36 and 38 such that the etching does not progress in a lateral direction. However, due to the anisotropic etching, it is difficult that only the insulating interlayer 32 (SiO2 or the like) is etched without etching a lower electrode layer (TiN, AlCu, Ti or the like) 26. In this case, Japanese Laid-Open patent publication No. 2002-319620 states that the formation of the etching delay layer 28 is particularly useful.
However, conventionally, there is room for improvement in the following points.
First, the etching for making the via is performed in twice in the semiconductor device manufacturing methods disclosed in Japanese Laid-Open patent publication Nos. 2002-190520 and 2000-235973. Therefore, the number of production processes and a process time are increased in making the via, and there is still room for improvement from the view points of productivity and the production stability.
Second, in the method of making the contact hole disclosed in Japanese Laid-Open patent publication No. 2002-319620, the resist 34, the insulating interlayer 32, and the etching delay layer 28 are sequentially etched to form the contact hole 36 which reaches an upper surface of the lower interconnection layer 26. However, because the lower interconnection layer 26 is exposed to a bottom portion of the contact hole 36, sometimes Al is eluted in a chemical solution in performing post-etching organic cleaning to the inside of the contact hole with the chemical solution when the lower interconnection layer 26 is made of AlSi. Thus, sometimes the metal elution of the lower interconnection layer 26 into the chemical solution causes a decrease in contact property between the lower interconnection and the via plug provided in the contact hole.